This application claims benefit of priority under 35 U.S.C. xc2xa7119 to Japanese Patent Application No. 2000-274222, filed on Sep. 8, 2000, the contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to ferroelectric memory devices for storing data in a nonvolatile manner by the use of ferroelectric capacitors, and, more particularly, to a ferroelectric memory device having a cell block formed of series-connected plural unit cells each including a parallel-connected ferroelectric capacitor and a memory cell transistor.
2. Description of Related Art
A ferroelectric memory device stores binary data in a nonvolatile manner in accordance with the value of remanent polarization of a ferroelectric capacitor. Generally, a memory cell of a conventional ferroelectric memory device is formed by series-connecting a ferroelectric capacitor and a transistor, as in the case of a DRAM. However, unlike a DRAM, a ferroelectric memory device stores data by remanent polarization. Accordingly, it is necessary to drive a plate line in order to read out a signal charge to a bit line. Therefore, a ferroelectric memory device requires a plate line driving circuit for driving a plate line. However, in a conventional ferroelectric memory device, a plate line driving circuit takes up significant space.
A cell array arrangement of a ferroelectric memory device, in which the area of a plate line driving circuit can be reduced, has been proposed by Takashima et al. In this arrangement, both sides of a ferroelectric capacitor (C) are connected to a source and a drain of a cell transistor (T) to form a unit cell, and a plurality of such unit cells are series-connected to form a cell block (D. Takashima et al., xe2x80x9cHigh-density chain ferroelectric random memory (CFeRAM)xe2x80x9d in Proc. VSLI Symp. June 1997, pp. 83-84). In this series connected TC unit type ferroelectric memory device, a plate line driving circuit can be shared by, e.g., eight unit cells. Therefore, a cell array can be highly integrated.
FIG. 24 shows a configuration of a memory cell array 1 of such a series connected TC unit type ferroelectric memory device. A unit cell MC consists of parallel-connected ferroelectric capacitor C and cell transistor T. In the example of FIG. 24, eight of such unit cells are series-connected to form a cell block MCB. FIG. 24 shows two cell blocks MCB0 and MCB1 connected to a pair of bit lines BBL and BL, respectively.
One end of the cell block MCB0 is connected to the bit line BBL via a block selecting transistor BST0 and one end of the cell block MCB1 is connected to the bit line BL via a block selecting transistor BST1. The other end of the cell block MCB0 is connected to a plate line BPL, and the other end of the cell block MCB1 is connected to a plate line PL. Gates of cell transistors in each cell block are connected to word lines WL0-WL7. A sense amplifier SA for sensing and amplifying read data is connected to the bit lines BL and BBL. Block selecting signals BS0 and BS1 are inputted to gates of the block selecting transistors BST0 and BST1, respectively.
FIG. 25 is a timing chart showing basic operations of such a ferroelectric memory device. In this case, a unit cell stores data as data xe2x80x9c1xe2x80x9d when the remanent polarization of the ferroelectric capacitor is in a positive state, and store data as data xe2x80x9c0xe2x80x9d when the remanent polarization of the ferroelectric capacitor is in a negative state. In a standby mode, all the word lines are held to be at xe2x80x9cHxe2x80x9d, the block selecting signals BS0, BS1 are held to be at xe2x80x9cLxe2x80x9d, and the bit lines BL, BBL and the plate lines PL, BPL are held to be at VSS (ground potential). At this time, the terminals of the ferroelectric capacitors C are shunted by the ON-state cell transistors so as to store data stably.
In an active mode, when a unit cell at the side of the bit line BL is selected by, e.g., the word line WL2, the bit line BL is held to be in a floating state to set the word line WL2 to be at xe2x80x9cLxe2x80x9d, and then, the block selecting signal BS1 is held to be at xe2x80x9cHxe2x80x9d, and the electric potential of the plate line PL is raised from VSS (ground potential) to VAA (positive potential). In this way, a voltage is applied to the ferroelectric capacitor of the selected unit cell, and a voltage signal is read to the bit line BL in accordance with whether the data is data xe2x80x9c0xe2x80x9d or data xe2x80x9c1xe2x80x9d.
The voltage signal read to the bit line BL is detected as a result of a comparison with a reference voltage Vref applied to the bit line BBL, which is paired with the bit line BL. That is, when a sense amplifier activating signal SE is raised, the sense amplifier SA sets the bit line BL to be at VAA if the data xe2x80x9c1xe2x80x9d is read, and at VSS if the data xe2x80x9c0xe2x80x9d is read. After that, by deactivating the sense amplifier SA, the read data is rewritten.
In these reading and rewriting operations, when the data xe2x80x9c1xe2x80x9d is read, a destructive read is performed, and when the data xe2x80x9c0xe2x80x9d is read, a nondestructive read is performed. That is, when the data xe2x80x9c1xe2x80x9d is read, the remanent polarization of the ferroelectric capacitor is remarkably reduced due to the addition of a positive voltage from the plate line PL, thereby causing a polarization reversal. After the reading operation, when the voltage of the plate line is lowered, since the bit line is held to be at a high potential by the read data, a reverse voltage of the voltage at the time of the reading operation is applied to the ferroelectric capacitor to perform the rewriting operation until the remanent polarization reaches the +Pr again. When the data xe2x80x9c0xe2x80x9d is read, no polarization reversal is caused by the plate line voltage. Further, no reversal voltage is applied after the reading operation. Therefore, the rewriting operation is performed while the remanent polarization remains negative.
In the above-described operations, the value of the read signal is determined by the capacitance of the bit line and the characteristic curves of the ferroelectric capacitor. FIG. 26 shows the relationship between the characteristic curves (hysteresis loop) and the value of the read signal. The positive voltage VAA supplied from the plate line side to the ferroelectric capacitor is shown as xe2x88x92VAA on the minus voltage axis, and the positive voltage VAA supplied from the bit line side to the ferroelectric capacitor is shown as VAA on the plus voltage axis. The bit line capacitance is shown as Cb. As shown in FIG. 26, the risings in potential of the bit line at the time of reading xe2x80x9c1xe2x80x9d data and xe2x80x9c0xe2x80x9d data can be obtained as the intersections of load lines having the inclination of xe2x88x92Cb and the hysteresis loop. In this case, the risings in voltage of the bit line are shown relative to xe2x88x92VAA.
As is apparent from FIG. 26, the read potentials of the xe2x80x9c1xe2x80x9d data and xe2x80x9c0xe2x80x9d data are lowered as the bit line capacitance Cb increases. Therefore, the read signal value, which is the difference between these potentials, also depends on the bit line capacitance Cb. Unlike a typical DRAM, the bit line capacitance dependency of the read signal value reaches the maximum value at a certain value of the bit line capacitance.
A series connected TC unit type ferroelectric memory device has a characteristic that the bit line load capacitance Cb differs depending on the position of the selected word line in the cell block. That is, if the case where a memory cell most distant from the bit line is selected by the word line WL7 is compared with the case where a memory cell closest to the bit line is selected by the word line WL0, the bit line capacitance is greater in the former case since the parasitic capacitances of the unit cells connected to the word lines WL0-WL6 are added as loads.
FIG. 27 shows that the bit line capacitance Cb substantially changes in accordance with the position of the selected word line, thereby changing the read signal value. The read signal potential is lower in the case of selecting the word line WL7 than the case of selecting the word line WL0 for both xe2x80x9c1xe2x80x9d data and xe2x80x9c0xe2x80x9d data.
When data is sensed, if one of the pair of bit lines BL, BBL is selected, the other is used as the reference bit line, to which a reference potential Vref is applied, as shown in FIG. 27. The reference potential Vref is set to be at the intermediate value between the read bit line potential in the case of xe2x80x9c1xe2x80x9d data and the read bit line potential in the case of xe2x80x9c0xe2x80x9d data. However, as is apparent from FIG. 27, in a series connected TC unit type ferroelectric memory device, if the reference potential Vref is set to be at a constant value, when the selected word line changes from WL0 to WL7, the difference between the read potential and the reference potential Vref is smaller in the case of xe2x80x9c1xe2x80x9d data, and bigger in the case of xe2x80x9c0xe2x80x9d data. FIG. 28 shows the relationship between the read potential and the position of the word line. The broken line in FIG. 28 represents the intermediate values between the read potentials in the cases of xe2x80x9c1xe2x80x9d data and xe2x80x9c0xe2x80x9d data.
As mentioned previously, in a series connected TC unit type ferroelectric memory device, the load capacitance-of the read memory cell changes in accordance with the position of the selected word line. This results in a problem that if the reference voltage Vref is set to be at a constant value, signal margins of xe2x80x9c0xe2x80x9d data and xe2x80x9c1xe2x80x9d data vary depending on the position of the accessed word line.
Given the above-described circumstances, an object of the present invention is to provide a series connected TC unit type ferroelectric memory device in which a substantially constant read signal margin can be obtained regardless of the word line position.
A ferroelectric memory device according to a first aspect of the present invention includes: a memory cell array in which a unit cell is formed of a ferroelectric capacitor a cell transistor, a source and a drain of the cell transistor being connected to both ends of the ferroelectric capacitor and a gate of the cell transistor being connected to a word line, and a cell block is formed by series-connecting a plurality of unit cells between a first terminal and a second terminal, the first terminal of the cell block being connected to a bit line via a block selecting transistor, and the second terminal of the cell block being connected to a plate line; a sense amplifier for sensing and amplifying a signal read from the ferroelectric capacitor of the unit cell to the bit line; a plate line driving circuit for driving the plate line; and an offset voltage applying circuit for, when data is read and before the sense amplifier is deactivated, applying to the bit line different offset voltages in accordance with the positions of the selected unit cells in the cell block.
In this way, by applying a different offset voltage to the bit line in accordance with the position of the selected unit cell, an imbalance in signal margin due to the parasitic capacitance in the cell block, which is a characteristic of a series connected TC unit type ferroelectric memory device, can be compensated.
A ferroelectric memory device according to a second aspect of the present invention includes: a memory cell array in which a unit cell is formed of a ferroelectric capacitor a cell transistor, a source and a drain of the cell transistor being connected to both ends of the ferroelectric capacitor and a gate of the cell transistor being connected to a word line, and a cell block is formed by series-connecting a plurality of unit cells between a first terminal and a second terminal, the first terminal of the cell block being connected to a bit line via a block selecting transistor, and the second terminal of the cell block being connected to a plate line; a sense amplifier for sensing and amplifying a signal read from the ferroelectric capacitor of the unit cell to the bit line; a plate line driving circuit for driving the plate line; and a precharge circuit for setting internal nodes of the cell block to be at a first potential which is somewhere between signal potentials of binary data read to the bit line in a standby mode.
A ferroelectric memory device according to a third aspect of the present invention includes: a memory cell array in which a unit cell is formed of a ferroelectric capacitor a cell transistor, a source and a drain of the cell transistor being connected to both ends of the ferroelectric capacitor and a gate of the cell transistor being connected to a word line, and a cell block is formed by series-connecting a plurality of unit cells between a first terminal and a second terminal, the first terminal of the cell block being connected to, a bit line via a block selecting transistor, and the second terminal of the cell block being connected to a plate line; a sense amplifier for sensing and amplifying a signal read from the ferroelectric capacitor of the unit cell to the bit line; a plate line driving circuit for driving the plate line; and a dummy cell block for, when data is read, applying a different parasitic capacitance to the reference bit line paired to the bit line to which the selected cell block is connected in accordance with the position of the selected unit cell.